As advances in semiconductor manufacturing technologies increase the number of transistors on a single die, computer architecture design focuses on increasing clock speeds. To reap the benefits of increased clock speeds, speed limitations associated with conventional logic must be overcome. In particular, evaluation time for synchronous logic must be reduced with increases in clock speed. Evaluation time is the time involved with generating a logical output in response to a logical input.
This continuous demand for performance improvement of integrated circuit (IC) chips has fueled the pervasive use of domino logic. When compared to conventional, complementary metal oxide semiconductor (CMOS) logic, domino logic offers high-speed operation, reduced die area, and reduced output capacitance.
Conventional domino logic includes a dynamic logic input circuit coupled with static gate circuits. A logic signal is received as an input on a first transition of a clock, and the signal is coupled to other circuitry and latched on the output on a next transition of the clock. More specifically, domino logic pre-charges a domino node, an input of the static circuitry, when a clock signal is low and couples the logic signal to the static circuitry via the dynamic logic input circuit when the clock signal is high. The dynamic logic input circuit often includes n-type metal oxide semiconductor (NMOS) transistors to pull down the voltage of the pre-charged, domino node. Then, an output circuit changes states in response to the low charge on the domino node to provide a stable output until the next clock cycle. Thus, the speed of domino logic is limited by the latencies involved with pre-charging the domino node, pulling down the pre-charged domino node voltage, and changing the state of the output circuit.
In addition, a keeper circuit is included in domino logic, compensating for leakage current, to maintain the pre-charge on the domino node. Leakage currents can cause an invalid evaluation when the domino node is discharged sufficiently by the leakage to change the output. The keeper circuit typically couples with the output and when the output indicates that the domino node is high, the keeper circuit is turned on to supply current to the domino node. The keeper circuit, however, increases evaluation time because the dynamic logic input circuit must not only pull down the pre-charge on the domino node but also the current supplied by the keeper circuit.
Solutions for reducing the latencies typically reduce the physical channel length of the circuit elements, the voltage supply for pre-charging the domino node, and the threshold voltages of selected transistors along a critical path within the domino circuit such as the threshold voltages of the transistors in the dynamic logic input circuit and the pull-up transistor in the output circuit. The short channel devices are able to change state over a smaller voltage % range more quickly by driving more current. However, the reduced threshold voltages and channel length of the transistors in the critical path result in higher subthreshold leakage currents. Thus, the keeper circuit must be sufficiently robust to handle the increased leakage currents, at the expense of increased evaluation time resulting from increased charge to be dissipated by the dynamic logic input circuit.
Further, the low threshold voltages along with faster signal edges increase problems associated with charge sharing and noise susceptibility. Charge sharing involves reduction of the voltage level at the domino node resulting from the capacitances associated with the domino node and the dynamic logic input circuit. Noise problems due to smaller geometry, often gauged by a measurement referred to as noise margin, result from noise coupling between, e.g., the inputs of the dynamic logic input circuit and the domino node. For instance, a noise introduced at the input of a low threshold voltage transistor in the dynamic logic input circuit may turn on the logic and drain current from the domino node, resulting in an invalid evaluation and output. Higher threshold voltage transistors can be implemented in the critical path through the domino circuit to compensate for higher noise, but such substitutions also increase evaluation time.